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一款NoC总线的低功耗设计

Low power design of NoC bus
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摘要 随着集成电路技术的飞速发展,其集成度和复杂度越来越高,导致芯片功耗问题日益严重。文章提出一套兼容片上网络(Net on Chip,NoC)总线的功耗管理总线,针对不同电源域进行低功耗管理,通过电源域开关协议将电源域状态同步到事务活动,且不影响系统其他部分的操作。实验结果表明,功耗管理总线具有低成本、协议简单、兼容性好、轻量级等优势。 With the rapid development of integrated circuit technology,its integration and complexity are becoming increasingly high,leading to increasingly serious power consumption issues in chips.This article proposes a power management bus that is compatible with the Net on Chip(NoC)bus,which performs low-power management for different power domains.The power domain status is synchronized to transaction activities through the power domain switch protocol,without affecting the operation of other parts of the system.The experimental results show that the power management bus has advantages such as low cost,simple protocol,good compatibility,and lightweight.
作者 徐新宇 陈玉蓉 张猛华 XU Xinyu;CHEN Yurong;ZHANG Menghua(The 54th Research Institute of China Electronics Technology Corporation,Wuxi,Jiangsu 214035,China)
出处 《计算机应用文摘》 2024年第5期44-46,共3页 Chinese Journal of Computer Application
关键词 NoC总线 低功耗 多电源域 协议 NoC bus low power consumption multiple power domains protocol
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  • 1高明伦,杜高明.NoC:下一代集成电路主流设计技术[J].微电子学,2006,36(4):461-466. 被引量:31
  • 2Keating M, Flynn D, Aiken R, et al. Low Power Methodology Manual for System-on-chip Design[M]. [S.l.]: Springer, 2007.
  • 3Savithri S, Lucie N, Rajendran E et al. A Timing Methodology Considering Within-die Clock Skew Variations[C]//Proc. of 2008 International SoC Conference. California, USA: [s. n.], 2008: 351-356.
  • 4Frenkil J.RTL techniques for optimizing power in SOC design[J].Computer Design, 1998; 1
  • 5M Pedram. Power minimization in IC Design :Principles and applications[J].ACM on Design Automation, 1996; 1 (1) :3~56
  • 6R Hossain,L D Wronshi,A Albieki.Low power design using double edge triggered flip-flops[J].IEEE Trans VLSI Systems,1994;2(2):261~265
  • 7Q Wu,M Pedram,X Wu.A new design of double edge triggered flip-flop[C].In:Proc ASP-DAC,1998:417~421
  • 8GUERRIER P, GREINER A. A generic architecture for onchip packet-switched [ C ] //Proc of Design Automation and Test in Europe Conf and Exhibition. Paris, France, 2000: 250-256.
  • 9HEMANI A, JANTSCH A, KUMAR S, et al. Network on chip : an architecture for billion transistor era [C]//Proc of the IEEE Norchip Conf. Turku, Finland, 2000: 166-173.
  • 10赵杰,李晨,邓玉良,周泽游.低功耗SOC的动态时钟管理[J].微电子学,2007,37(5):735-738. 被引量:3

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