基于FPGA的方位预滤波设计

An Azimuth Pre-Filering Design Based on FPGA

本文结合某项目工程需要,介绍了一种SAR成像预滤波处理方法,在FPGA中通过外部QDRII存储芯片实现了PRT级数据流缓存,利用FPGA强大的并行处理能力完成FDC补偿以及SAR成像预滤波算法的计算,并将预滤波所有参数通过DSP控制,既缩短了运算时间,又提高了调试效率,实现了一块3U板卡完成整个SAR雷达信号处理。

An SAR pre-filtering method was proposed in some paper to meet engineering requirement of some projects.The data streaming of PRT-grade in FPGA was realized via outside QDRII SDRAM caches;fdc compensation and SAR pre-filtering calculation were accomplished by using the powerful parallel processing capabilities of FPGA;all parameters with pre-filtering correlation were setting by DSP.Thanks to the above-mentioned methods,the calculating time was reduced,debugging efficiency was improved,and the SAR radar signal process in one 3U board was accomplished.