申威众核处理器访存与通信融合编译优化

Memory Access and Communication Fusion Compiler Optimization for Sunway Many-core Processors

申威众核片上多级存储层次是缓解众核“访存墙”的重要结构.完全由软件管理的SPM结构和片上RMA通信机制给应用性能提升带来很多机会,但也给应用程序开发优化与移植提出了很大挑战.为充分挖掘片上存储层次特点提升应用程序性能,同时减轻用户编程优化负担,提出一种多级存储层次访存与通信融合的编译优化方法.该方法首先设计融合编译指示,将程序高层信息传递给编译器.其次构建编译优化收益模型并设计启发式循环优化方案迭代求解框架,并由编译器完成循环优化方案的求解和优化代码的变换.通过编译生成的DMA和RMA批量数据传输操作,将较低存储层次空间中高访问延迟的核心数据批量缓冲进低访问延迟的更高存储层次空间中.在3个典型测试用例上进行优化实验测试与分析,结果表明所提出的优化在性能上与手工优化相当,较未优化版程序性能有显著提升.

The on-chip memory hierarchy of Sunway many-core processors is an important structure to alleviate the many-core“memory access wall”.The SPM structure and on-chip RMA communication mechanism completely managed by software bring many opportunities for improving application performance but also pose great challenges for development optimization and porting of applications.To fully explore the hierarchical features of on-chip memory,improve application performance,and reduce the burden of user programming optimization,this study proposes a compiler optimization method that integrates multi-level memory access and communication.This method first designs a fusion compiler directive to transfer high-level information of the program to the compiler.Secondly,a compiler optimization revenue model is built and an iterative solution framework of a heuristic loop optimization scheme is designed.Meanwhile,the compiler completes the solution and code transformation of the loop optimization scheme.DMA and RMA batch data transmission operations are generated by compilation,batch buffer core data with high access latency from lower storage hierarchy spaces into higher storage hierarchy spaces with low access latency.Optimization experiments and analysis are conducted on three typical test cases,and the results show that the program performance optimized by this method is comparable to manual optimization,and significantly improves compared to the unoptimized version.