基于FPGA的分段近似双边滤波算法设计与实现

Design and implementation of piecewise approximation bilateral filtering algorithm based on FPGA

为了增强图像显示的质量以及减少基于现场可编程逻辑器件(FPGA)双边滤波算法中硬件资源的消耗,设计了一种分段近似的双边滤波算法。通过分段近似计算减少了双边滤波中值域的存储容量以及输出的数据位宽,从而降低了计算复杂度和硬件资源消耗。在Zynq-7000和Sparten-7的FPGA平台上实现了分段近似的双边滤波算法,研究了不同高斯噪声及在其最佳的值域标准差下的滤波和边缘保持性能。结果表明,本文算法在性能上与传统的双边滤波算法相当,并且与传统的双边滤波算法相比,其查找表(LUT)和数字信号处理模块(DSP)的使用量减少了9.9%和71.1%,且功耗仅为0.128 W。本文算法适合用于硬件资源有限的图像滤波应用场景。

In order to enhance the quality of image display and reduce the consumption of hardware resources in the bilateral filtering algorithm based on field programmable logic devices(FPGAs),a piecewise approximation bilateral filtering algorithm is designed.The piecewise approximation reduces the storage capacity of the range domain and the bit width of the output data in bilateral filtering,thus reducing the computational complexity and hardware resource consumption.The bilateral filtering algorithm of piecewise approximation is implemented on the FPGA platform of Zynq-7000 and Sparten-7,and the performance of filtering and edge preserving under different Gaussian noise and its optimal range standard deviation is studied.The results show that the performance is comparable to that of the traditional bilateral filtering algorithm,the use of look-up table(LUT)and digital signal processing module(DSP)is reduced by 9.9%and 71.1%compared to the conventional bilateral filtering algorithm,and the power consumption is only 0.128 W.The algorithm is suitable for image filtering application scenarios with limited hardware resources.