适用于嵌入式五口SRAM的多频率内建自测电路

A Multi-frequency BIST IP Core with Scan Chain for Embedded Register File

提出了一种多频率带有扫描链的 BIST方案 ,用于五口的 32× 32嵌入式 SRAM的可测性设计。分析了多口 SRAM的结构并确定其故障模型 ,在此基础上提出了一种名为“对角线移动变反法”( OMOVI)的新算法及其电路实现。与传统的“移动变反法”( MOVI)相比 ,在保证故障覆盖率前提下 ,测试图形的测试步数由原来的12 N log2 N减小为 N/ 2 +2 N log2 N( N为 SRAM的容量 )。该方案集功能测试、动态参数提取和故障分析定位于一体 。

A multifrequency BIST design with scan chain presented here supports the 32 word by 32 bit, five po rt embedded register file which can perf orm simultaneous and independent reads a nd writes. We considered the special fau lt models for the complex structure of t he register file. A new algorithm named diagonal moving inversion and BIST circu it are created, which needs only N /2+2 N log 2 N operations but can achieve t he high fault coverage. This BIST design integrates functional test, dynamic par ameter capture and diagnosis together an d is flexible for all kinds of register files.