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Parallelized Hashing via <i>j</i>-Lanes and <i>j</i>-Pointers Tree Modes, with Applications to SHA-256

Parallelized Hashing via <i>j</i>-Lanes and <i>j</i>-Pointers Tree Modes, with Applications to SHA-256
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摘要 j-lanes tree hashing is a tree mode that splits an input message into?j?slices, computes?j?independent digests of each slice, and outputs the hash value of their concatenation.?j-pointers tree hashing is a similar tree mode that receives, as input,?j?pointers to?j?messages (or slices of a single message), computes their digests and outputs the hash value of their concatenation. Such modes expose parallelization opportunities in a hashing process that is otherwise serial by nature. As a result, they have a performance advantage on modern processor architectures. This paper provides precise specifications for these hashing modes, proposes appropriate IVs, and demonstrates their performance on the latest processors. Our hope is that it would be useful for standardization of these modes. j-lanes tree hashing is a tree mode that splits an input message into?j?slices, computes?j?independent digests of each slice, and outputs the hash value of their concatenation.?j-pointers tree hashing is a similar tree mode that receives, as input,?j?pointers to?j?messages (or slices of a single message), computes their digests and outputs the hash value of their concatenation. Such modes expose parallelization opportunities in a hashing process that is otherwise serial by nature. As a result, they have a performance advantage on modern processor architectures. This paper provides precise specifications for these hashing modes, proposes appropriate IVs, and demonstrates their performance on the latest processors. Our hope is that it would be useful for standardization of these modes.
作者 Shay Gueron
出处 《Journal of Information Security》 2014年第3期91-113,共23页 信息安全(英文)
关键词 TREE Mode HASHING SHA-256 SIMD Architecture Advanced Vector Extensions Architectures AVX AVX2 Tree Mode Hashing SHA-256 SIMD Architecture Advanced Vector Extensions Architectures AVX AVX2
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