超大规模集成电路宏模块布局研究进展

Survey of VLSI Macro Placement

宏模块布局是超大规模集成电路(very large scale integration,VLSI)物理设计的核心环节之一,对集成电路的性能有重大影响。随着越来越多的知识产权核和其他预先设计的宏模块被广泛采用,VLSI通常集成数百个甚至上千个宏模块,给其布局带来了巨大挑战。基于此,聚焦VLSI宏模块布局研究,首先介绍VLSI布局的研究背景;其次阐述2D宏模块布局算法的主要类型和发展,包括基于解析和基于打包的2D宏模块布局算法;最后探讨宏模块布局未来的研究趋势,主要包括3D宏模块布局和基于机器学习的宏模块布局方法。

Macro placement is a crucial stage of physical design in very large scale integration(VLSI),which significantly impacts the performance metrics.With the widespread utilization of intellectual property and pre-designed macros,advanced VLSI designs typically integrate hundreds or even thousands of macros,posing significant challenges to VLSI placement.This paper focuses on the research of VLSI macro placement.Firstly,it introduces the research background.Secondly,it discusses two-dimensional(2D)macro placement methods,including analytical-based and packing-based approaches.Finally,the paper explores the future research trends of macro placement,including three-dimensional(3D)macro placement and machine learning-based approaches.