一种基于时间寄存型脉宽比较器和离散时间微分器的无采样时钟准数字FSK解调器

Sampling-clockless quasi-digital FSK demodulator implemented with time-register-based pulse-width comparators and a discrete-time differentiator

本文提出并实现了一种高载波频偏抑制、无采样时钟的准数字频移键控(FSK)解调器。解调器采用了一种对工艺、温度和电压等变化具有较好鲁棒性的准数字时间寄存器构造成脉宽比较器,无需高频采样时钟便可对FSK信号的载波周期进行精确鉴别从而实现信号的解调。同时在解调器中集成了一种离散时间微分器,可有效地抑制FSK信号载波频率偏差和漂移对解调性能的影响。本文完成了解调器的原型设计、原理分析、制作和测试。测试结果显示解调器只需最低10.7 dB的信噪比,便可对调频系数0.5、数据率1 Mpbs的FSK信号实现解调(误码率不超过10),同时能够对-0.56~0.48 MHz范围内变化的载波频偏和频漂进行有效抑制。

This article proposes and implements a sampling-clockless quasi-digital frequency-key-shifting(FSK)demodulator with a strong tolerance against carrier-frequency offset.To precisely discriminate periods of the FSK signal without a high-frequency sampling clock,quasi-digital time registers are used to construct pulse-width comparators(PWC)to demodulate the FSK signal,which are robust against the process,voltage,and temperature variation.In addition,a discrete-time differentiator is proposed and integrated into the demodulator to efficiently reject the inevitable carrier frequency offset and drift of the FSK signal.The demodulator is prototyped,analyzed,implemented,and tested.The measurement results show that the demodulator can demodulate FSK signal with a data rate of 1 Mbps and a modulation index of 0.5,while only requiring a 10.7 dB signal-to-noise ratio to achieve a demodulation quality with a bit-error ratio of no more than 10while tolerating a frequency offset or drift in the range of-0.56 to 0.48 MHz.