基于FPGA的“龙鳞”通信模块跨时钟域验证实践

Cross-Clock Domain Verification Practice of NASPIC Communication Module Based on FPGA

由于现场可编程逻辑门阵列(FPGA)功能实现的多元化,往往会出现不同时钟域的信号.不同时钟域的信号进行交互,若不进行同步处理,经常会产生数据丢失、时序错误等问题,所以跨时钟域检查对FPGA功能实现特别重要.本文主要阐述了在开展"龙鳞"平台通信模块FPGA软件验证与确认工作中跨时钟域检查的测试流程和方法,对跨时钟异常进行分类,分析通信模块FPGA软件的跨时钟异常并提供解决方案,为FPGA测试工程师提供一种测试思路.

Different clock domain signals often appear due to the diversification of field programmable gate array(FPGA)functions.Signals from different clock domains interact with each other.Data loss,timing errors and other problems often occur without synchronous processing.Therefore,cross-clock domain checking is especially important for FPGA function realization.This paper mainly describes the testing process and method of cross-clock domain checking in the verification and validation of FPGA software for nuclear advanced safety platform of I&C(NASPIC)communication module.It classifies the cross-clock domain exceptions,analyzes the exceptions of FPGA software for communication module and presents solutions,and provides a test idea for FPGA test engineers.