一种高速低功耗8 bit两步式SAR ADC的设计

An 8-bit 1GS/s two-step high-speed and low-power SAR ADC

近年来,随着5G通信技术以及物联网技术的兴起,人们对高速、低功耗ADC的需求日益增长,对其性能要求也越来越高,传统SAR ADC结构为实现高转换速度需要以降低转换精度为代价,目前同时实现高速度和高精度仍是其设计难点。为实现高性能SARADC设计,本文基于电压-时间混合域量化结构,采用2bits/cycle技术,以锁存器为辅,有效减小单个比较周期所需时长。采用级间冗余技术,通过数字逻辑提供0.5位冗余并使第2级时间域的量化精度提升0.5位。本文基于TSMC65-nmCMOS工艺进行电路设计,最终实现1GS/s采样率、8.5比特量化位数、功耗为3.6m W、SNDR为49.89dB,Fo M为14.1 fJ/conv.-step的高速低功耗SAR ADC的设计。

In recent years,with the emergence of 5G communication technology and internet of things(IoT)technology,the demand for high-speed and low-power ADCs has been increasing.The performance requirements for these ADCs are also getting higher.Traditional successive approximation register(SAR)ADC structures achieve high conversion speeds at the cost of reduced conversion accuracy,and currently,achieving both high speed and high accuracy remains a design challenge.In order to achieve high-performance SAR ADC design,this paper proposes a voltage-time hybrid domain quantization structure and adopts the 2bits/cycle technique with the assistance of latch,effectively reducing the required duration of a single quantization cycle.The inter-stage redundancy technique is used to provide 0.5 bits of redundancy through digital logic,improving the quantization accuracy of the second stage in the time domain by 0.5 bits.This article is based on the TSMC 65-nm CMOS process for circuit design,achieving a high-speed and low-power SAR ADC with a sampling rate of 1 GS/s,a quantization bit number of 8.5,a power consumption of 3.6 mW,an SNDR of 49.89 dB,and a FoM of 14.1 fJ/conv.-step.