用于EEG信号传感的低功耗LC-ADC设计

Design of low power LC-ADC for EEG signal sensing

与穿戴式设备相比,植入式脑机接口芯片具有检测精度高、抗干扰等优点,但实际患者使用时的终生长待机问题仍是系统设计的难点。本文提出一种用于植入式脑电信号传感的超低功耗水平交叉式模拟数字转换器电路,结构中采用MOS管伪电容以减少版图面积并简化1-bit电容型数字模拟转换器的模块结构;设计三输入静态比较器减少传统LC-ADC双比较器结构的冗余功耗;在逻辑控制模块加入双边延迟电路,使伪电容有效达到高低阈值电压,通过提高其充放电精度提升整体ADC系统的转换精度。采用SMIC 0.18μm标准CMOS工艺完成电路设计,Cadence仿真实验结果表明,在电源电压为0.9 V,输入为10 Hz正弦波的条件下,LC-ADC的平均功耗为662 nW,有效转换位数(ENOB)为5.49 bit,信噪比为(SNR)为34.83 dB,杂散动态范围(SFDR)为43.94 dBc。

Compared with the wearable devices,implantable brain-computer interface technology has the advantages in terms of high detection accuracy and anti-interference,and however the problem of lifetime power standby is still a difficulty in system design.This paper proposes an ultralow-power level-crossing analog-to-digital converters(LC-ADC)circuit for electroencephalogram signal sensing,which employs a pseudo-capacitor connected by MOS transistors to greatly reduce the layout area and simplify the structure of a 1-bit CDAC;The use of a three-input static comparator reduces redundant power consumption in a traditional LC-ADC dual comparator architecture;The addition of bilateral delay circuit into the logic control block enables the pseudo-capacitor to achieve high and low threshold voltages respectively to improve the accuracy of the pseudo-capacitor charge and discharge,thereby improving the accuracy of the overall LC-ADC system.The circuit is designed by SMIC 180μm CMOS technology and the Cadence-based simulation results show that,on the conditions of 0.9 V power supply voltage and 10 Hz input sine wave,the average power consumption of the LC-ADC circuit is 662 nW,the effective number of bits(ENOB)is 5.49 bit,the signal to noise ratio(SNR)is 34.83 dB and the spurious dynamic range(SFDR)is 43.94 dBc.