基于Xilinx 7系列FPGA的频域均衡器

Frequency Domain Equalizer Based on Xilinx 7 Series FPGA

介绍了一种频域均衡器在Xilinx 7系列FPGA上的实现方法,此方法基于迫零均衡算法,并使用FFT IP核简化逻辑设计。仿真测试证明,使用该方法设计的均衡器相对Matlab浮点计算结果具有不高于0. 66‰的误差,能够有效地消除通信信号中由信道衰落引起的误差,提高无线通信系统的误码性能。本文所介绍的设计方法为无线通信系统中频域均衡器的FPGA设计提供了有效参考。

This paper describes a method of implementing a frequency domain equalizer on a Xilinx 7-series FPGA. This method is based on the zero-forcing equalization algorithm. FFT IP cores are used to simplify the logic design. Simulations show that comparing to the floating-point calculation result from Matlab,the output of the equalizer designed based on the proposed method has a relative error of no more than 0. 66‰. So the equalizer can effectively compensate the error in the signal in a wireless communication system caused by channel fading,and improve the bit error performance of the system. The proposed method provides an effective reference for FPGA design of frequency domain equalizer in wireless communication systems.