CMOS图像传感器列并行单斜式ADC回踢噪声自补偿方法

Self-Compensation Method for Kickback Noise of CMOS Image Sensor Column Parallel Ramp ADC

提出了一种用于CMOS图像传感器的列并行单斜式ADC(analog-to-digital converter)回踢噪声自补偿方法,有效抑制了量化比较器对高精度共享斜坡的回踢与串扰。为了消除原始节点的回踢噪声,通过检测列级斜坡信号的突变来补偿列间共享斜坡信号线的串扰,阻断噪声在共享斜坡信号线上的传输。采用本文提出的方法,基于55 nm 1P4M CMOS工艺,完成了3072(H)×2560(V)CMOS图像传感器芯片的设计与实验,该传感器实现了12位精度的列并行数字量化。当同时翻转100到1000列时,在最坏的情况下,回踢噪声可以降低到1 LSB以下,并在不增加功耗和面积的情况下实现了自补偿。测量结果表明,该单斜式ADC工作频率为500 MHz,12位线性A/D转换的数字相关双采样行时间为4.6μs,DNL控制在±0.48 LSB以内,INL不大于±4 LSB,信噪比高达71 dB。重要的是,每列的功耗仅为24μW。

A new CMOS image sensor column parallel ADC(analog-to-digital converter)circuit structure for suppressing the kickback noise of the single slope comparators is proposed in this paper.In order to suppress the kickback noise of the original node,the crosstalk of the shared ramp reference is compensated by detecting the column ramp signal jumping,and the transmission of the noise on the shared reference line is blocked.The proposed approach has been verified and experimented in a 3072(H)×2560(V)CMOS image sensor based on 55 nm 1P4M CMOS process,and the sensor achieves 12 bit precision column parallel digital quantization.When 100 to 1000 columns are flipped simultaneously,the kickback noise can be reduced to less than 1LSB and compensated quickly without additional power consumption and area in the worst case.The measurement results show that the single slope ADC can be operated at 500 MHz and achieved 4.6μs digital correlated double sampling row time for a 12 bit linear A/D conversion,the DNL is controlled within±0.48 LSB,the INL is not more than±4 LSB,and the SNR is up to 71 dB.It is important that the power consumption of each column is only 24μW.