期刊文献+

功率集成电路TID加固环栅器件研究现状综述

An Overview of the Research on TID Radiation-Hardened Enclosed Layout Devices for Power Integrated Circuits
下载PDF
导出
摘要 总结了标准工艺下功率集成电路中总剂量辐射(TID)加固环栅MOS器件与环栅功率器件的研究现状,归纳了不同结构形态的环栅器件的性能优劣,推荐8字形环栅MOS器件、华夫饼功率器件及回字形LDMOS器件结构用于功率集成电路的TID加固设计。同时,阐述了现有环栅MOS器件等效W/L的建模情况,提出保角变换是环栅MOS器件等效W/L精确建模的重要方法,最后还给出了环栅器件建库的基本流程。 The researches on total ionizing dose radiation-hardened enclosed layout MOS and enclosed layout power device in power integrated circuits under standard processes were summarized.The advantage and disadvantage performances of different structural forms of radiation-hardened enclosed layout devices was analyzed.8-shaped enclosed layout MOS,waffle typed layout power MOS and rectangular-shape LDMOS were recommended in power integrated circuit design.The modeling of equivalent W/L of existing radiation-hardened enclosed layout MOS devices were elaborated.Conformal transformation was an important way for accurate modeling of equivalent W/L of enclosed layout MOS devices.Finally,the basic process for building a library of enclosed layout devices was provided.
作者 罗萍 吴昱操 范佳航 张致远 冯皆凯 赵忠 LUO Ping;WU Yucao;FAN Jiahang;ZHANG Zhiyuan;FENG Jiekai;ZHAO Zhong(State Key Lab.of Elec.Thin Films and Integr.Dev.,Univ.of Elec.Sci.and Technol.of China,Chengdu 610054,P.R.China;Chongqing Institute of Microelec.Industry Technol.,Univ.of Elec.Sci.and Technol.of China,Chongqing 400060P.R.China)
出处 《微电子学》 CAS 北大核心 2023年第6期957-964,共8页 Microelectronics
基金 重庆市自然科学基金资助项目(CSTB2023NSCQMSX0153)
关键词 总剂量辐射加固 环栅MOS器件 环栅功率MOS 等效W/L建模 环栅器件建库 total ionizing dose radiation-hardened enclosed layout MOS device enclosed layout power MOS equivalent W/L modeling building library of enclosed layout device
  • 相关文献

参考文献11

二级参考文献36

  • 1何宝平,陈伟,王桂珍.CMOS器件^(60)Coγ射线、电子和质子电离辐射损伤比较[J].物理学报,2006,55(7):3546-3551. 被引量:15
  • 2陈志勇,黄其煜,龚大卫.BCD工艺概述[J].半导体技术,2006,31(9):641-644. 被引量:7
  • 3李冬梅,王志华,皇甫丽英,勾秋静,雷有华,李国林.NMOS晶体管高剂量率下总剂量辐照特性研究[J].电子器件,2007,30(3):748-751. 被引量:4
  • 4郭天雷,赵发展,刘刚,李多力,李晶,赵立新,周小茵,海潮和,韩郑生.Total Dose Radiation Hardened PDSOI CMOS 64k SRAMs[J].Journal of Semiconductors,2007,28(8):1184-1186. 被引量:1
  • 5Faccio F, Cervelli G. Radiation-induced edge effects in deep submicron CMOS transistor. IEEE Trans Nucl Sci, 2005, 52(6): 2413.
  • 6Li Dongmei, Huangfu Liying, Gou Qiujing, et al. Total ionizing dose radiation effects on MOS transistors with different layouts. Chinese Journal of Semiconductors, 2007, 28(2): 171.
  • 7Lacoe R, Osborn J, Koga R, et al. Application of hardness- by-design methodology to radiation-tolerant ASIC technologies. IEEE Trans Nucl Sci, 2000, 47(6): 2334.
  • 8Lacoe R. Improving integrated circuit performance through the application of hardness-by-design methodology. IEEE Trans Nucl Sci, 2008, 55(4): 1903.
  • 9Dodd P, Shaneyfelt M, Schwank J R, et al. Current and future challenges in radiation effects on CMOS electronics. IEEE Trans Nucl Sci, 2010, 57(4): 1747.
  • 10Snoeys W, Faccio F, Burns M, et al. Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel detector readout chip. Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2000, 439(2/3): 349.

共引文献18

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部