一种宽电源范围时钟IP设计

Design of a Clock IP with Wide Power Supply Range

提出了一种适用于1.8/2.5/3.3 V宽电源范围的时钟IP电路结构。为了抑制电源变化时鉴频鉴相器(PFD)复位脉冲信号对电荷泵(CP)性能所产生的影响,提出了一种恒定复位脉宽产生电路结构。采用超低失配CP,增加输出电流匹配性,当控制电压在0.2~(V_(DD)-0.2)V范围内变化时,I_(UP)/I_(DN)电流失配小于0.09%。引入对称负载结构环形振荡器(RO),抑制电源变化对环路性能所产生的影响。基于SMIC 180 nm CMOS工艺,完成整体电路设计与仿真,输出频率为100~500 MHz。仿真结果显示,当输入参考频率为50 MHz、输出频率为250 MHz时,在1.8/2.5/3.3 V电源电压下,功耗分别为8.2/12.5/18.4 mW,参考杂散低于-74 dBc,输出均方根抖动为1.8 ps。

A clock IP circuit structure suitable for 1.8/2.5/3.3 V wide power supply range is proposed.In order to suppress the influence of the reset pulse signal of the frequency and phase detector(PFD)on the performance of the charge pump(CP)when the power supply changes,a constant reset pulse width generation circuit is proposed.An ultra-low mismatch CP was used to increase the output current matching.The I_(UP)/I_(DN)current mismatch was less than 0.09%when the control voltage varied within a range of 0.2-(V_(DD)-0.2)V.At the same time,a ring oscillator(RO)with symmetrical load structure was introduced to suppress the impact of power supply change on the loop performance.The whole circuit was designed and simulated in SMIC 180 nm CMOS process,and the output frequency was 100-500 MHz.The simulation results show that when the input reference frequency is 50 MHz and the output frequency is 250 MHz,the power consumption is 8.2/12.5/18.4 mW at 1.8/2.5/3.3 V supply voltage,respectively,the reference spurious is lower than-74 dBc,and the output rms jitter is 1.8 ps.