增量型Σ-Δ调制器优化设计算法研究

Research on Optimal Design Algorithm of IncrementalΣ-ΔModulator

提出了一种用于增量型Σ-ΔADC的调制器设计的算法。该算法针对增量型Σ-ΔADC中的积分器系数进行优化,采用两步式搜索的方法,对可能的最优解组合进行多次求解与对比分析。基于该算法,设计了一种16位40 kS/s增量型Σ-ΔADC。可以对ADC电路的有效精度和输入采样速率这两个性能指标进行有效调节及优化。仿真结果表明,采用所提出的优化设计算法可以将ADC的输入采样速度由40 kS/s提升到51 kS/s,或者将ADC的ENOB由13.76 bit提高到14.72 bit,且不增加额外功耗。

A parameter optimization algorithm for the incrementalΣ-Δmodulator is proposed.The coefficient of the integrator in the incrementalΣ-Δmodulator was optimized.The two-step search algorithm was proposed to solve and compare the possible optimal coefficient combination for many times.Based on this algorithm,the effective precision and the input sampling rate of theΣ-ΔADC could be effectively adjusted and optimized.An 16 bit 40 kS/s incrementalΣ-ΔADC was designed.The simulation results show that the proposed optimization design algorithm can increase the ADC input sampling speed from 40 kS/s to 51 kS/s,or increase the ADC ENOB from 13.76 bit to 14.72 bit without adding additional power consumption.