一种电阻串加内插结构的16位D/A转换器

A 16-bit D/A Converter Based on Resistor String and Interpolation

设计了一种10位电阻串分压加6位内插结构的16位电压输出型D/A转换器。高10位采用1024个电阻串分压网络,低6位采用64个运放输入级内插结构,均采用温度计的方式进行线性叠加,从结构上保证了16位D/A转换器的单调性。该D/A转换器的输出运放采用了PMOS输入折叠式共源共栅加Class AB输出缓冲结构、多级嵌套式密勒补偿(NMCNR),实现了高直流增益和大电容负载下的稳定性。该16位D/A转换器基于0.6μm CMOS工艺设计,在5 V电源电压下,仿真结果表明,微分非线性误差为0.35 LSB,积分非线性误差为3.05 LSB,建立时间为6.12μs,无杂散度动态范围(SFDR)为93.41 dB,功耗为1.84 mW。在接470 pF电容负载的条件下,输出运放直流增益为150.63 dB,单位增益带宽为1.59 MHz,相位裕度为65.84°。

A 16-bit voltage output type digital-to-analog converter(DAC)with 10-bit resistor string divider and 6-bit interpolation structure was designed.The high 10-bit element consisted of a 1024 resistors string voltage divider network.The lower 6-bit element was made of 64 op-amp input stage interpolation structure.Both of them were linearly superimposed by thermometer,which structurally ensured the monotonicity of the 16-bit D/A converter.The output amplifier of the D/A converter adopted PMOS input folded cascode,Class AB output buffer structure and multi-stage nested Miller compensation(NMCNR).The stability under high DC gain and large capacitance load was realized.The 16-bit D/A converter was designed in a 0.6μm CMOS process.The supply voltage was set at 5 V.The simulation results show that the differential nonlinear error(DNL)is 0.35 LSB,the integral nonlinear error(INL)is 3.05 LSB,the set-up time is 6.12μs,the spurious-free dynamic range(SFDR)is 93.41 dB,and the power consumption is 1.842 mW.With a 470 pF capacitor load,the output op-amp DC gain is 150.63 dB,the unit gain bandwidth is 1.59 MHz,and the phase margin is 65.84°.