一种消除模拟TOF阵列探测器FPN的两级CDS电路

A Two-Stage CDS Circuit for Eliminating FPN in Analog TOF Array Detector

提出了一种新颖的两级相关双采样(CDS)电路,用于消除基于时间幅度转换器(TAC)结构的高密度光子飞行时间(TOF)阵列探测器的固定模式噪声(FPN)。相比于传统的全差分电路,该电路的结构更加简单,每一级仅使用两个开关管和一个采样电容。电路采用SMIC 0.18μm标准CMOS工艺制造,面积仅为40μm×35μm,静态功耗仅为301μW。测试结果表明,所提出的两级CDS电路具有99.98%的高线性度,在1.8 V电源下实现了0.9 V的宽输出摆幅,FPN总量减少了54%以上。提出的CDS方案可以有效消除阵列的像素级和列级的FPN,非常适用于基于TAC的高密度TOF阵列探测器。

A novel two-stage correlation double sampling(CDS)circuit is proposed to remove the fixed pattern noise(FPN)for a compact time of flight(TOF)array detector with the time-amplitude converter(TAC)structure.Each CDS stage only adopted two switch transistors and one sampling capacitor,which was much simpler than the traditional fully differential ones.Fabricated in SMIC 0.18μm standard CMOS technology,the CDS circuit merely occupied a small area of 40μm×35μm and consumed the low static power of 301μW.Experimental results show that the proposed two-stage CDS circuit has a high linearity of 99.98%and a wide output swing of 0.9Vunder 1.8Vsupply.The total FPN is reduced by more than 54%.The proposed CDS scheme can effectively eliminate the FPN from the pixels and column lines on the array,which is very suitable for high-density TAC-based TOF detectors.