一种自适应可重构宽带低抖动锁相环时钟

A Wideband Low Jitter PLL Clock with Adaptive Reconfigurable Charge Pump

为满足不同速率的串行收发数据采样需求,基于可重构电荷泵阵列设计了一种低抖动宽带锁相环时钟。根据锁相环倍频系数,自适应匹配电荷泵阵列输出电流,实现了较宽频率变换的低抖动输出时钟。锁相环时钟采用40 nm CMOS工艺设计,面积为367.227*569.344μm^(2)。测试结果表明,锁相环调谐范围为1~4 GHz,输出时钟均方根抖动为3.01 ps@1.25 GHz和3.98 ps@4 GHz,峰峰值抖动小于0.1UI。

In order to meet the sampling requirements of serial transceiver data with different rates,a wideband low jitter PLL clock was designed based on the reconfigurable charge pump array.To realize low jitter clock output with wide frequency range,the output current of the charge pump array was adaptively matched according to the PLL frequency-multiplier factor.The PLL was designed in a 40nm CMOS process,and the area was 367*569μm^(2).The experimental results show that the tuning range of the PLL is 1~4GHz,the clock output RMS jitter is 3.01ps@1.25GHz and 3.98ps@4GHz,and the peak-peak jitter is less than 0.1UI.