基于FPGA的二值忆阻器仿真器研究及应用

Research and Application of FPGA-Based Binary Memristor Emulator

基于FPGA的可重构性,提出了一种基于数字电路的二值忆阻器仿真器。与模拟电路忆阻器仿真器相比,所提出基于数字电路的忆阻器仿真器易于重新配置,与它所基于的数学模型表现出很好的匹配性,符合忆阻器仿真器所有要求的特点。实现了基于该仿真器的与门、或门、加法器及三人表决器。使用Altera Quartus II和ModelSim工具对仿真器功能和基于该仿真器实现的逻辑电路进行验证。给出所有设计电路的原理图、仿真结果和FPGA资源消耗。仿真结果表明,该二值忆阻器仿真器相比其他数字电路忆阻器仿真器具有更少的硬件资源消耗,更适合用于大规模忆阻器阵列研究。

Based on the reconfigurability of FPGAs,a digital circuit-based binary memristor emulator is proposed.Compared with the analog circuit-based memristor emulator,the proposed digital circuit-based memristor emulator was easier to reconfigure and was in good match with the mathematical model on which it was based,which could meet all the required characteristics of a memristor emulator.The and-gate,or-gate,adder,and three-person voter were implemented based on this emulator,and the functions of the emulator and the logic circuits were verified by the Altera Quartus II and ModelSim tools.Furthermore,the circuit schematics,simulations results and FPGA resource consumption were given for all designs.According to the simulation results,this binary memristor emulator has smaller hardware resource consumption and is more suitable for the study of large-scale memristor arrays than other digital circuit-based memristor emulators.