一种面向可容错应用的低功耗SRAM架构

A Low Power SRAM Architecture for Error-Tolerant Applications

提出了一种面向可容错应用的低功耗SRAM架构。通过对输入数据进行预编码,提出的SRAM架构实现了以较小的精度损失降低SRAM电路功耗。设计了一种单端的8管SRAM单元。该8管单元采用读缓冲结构,提升了读稳定性。采用打破反馈环技术,提升了写能力。以该8管单元作为存储单元的近似SRAM电路能够在超低压下稳定工作。在40 nm CMOS工艺下对电路进行仿真。结果表明,该8管单元具有良好的稳定性和极低的功耗。因此,以该8管单元作为存储单元的近似SRAM电路具有非常低的功耗。在0.5 V电源电压和相同工作频率下,该近似SRAM电路的功耗比采用传统6管单元的SRAM电路功耗降低了59.86%。

A low power SRAM architecture for error-tolerant applications is proposed.By pre-coding the input data,the proposed SRAM architecture reduced the power consumption of SRAM circuit with acceptable loss of precision.A single-ended 8T(SE-8T)SRAM bit cell was designed.The proposed SE-8Tcell improve read stability by the using of a read buffer.The write ability of SE-8Twas improved by breaking the feedback loop of the cell.Cooperated with the SE-8T,the approximate SRAM worked well under ultra-low supply voltage.The proposed SRAM circuit was simulated in the 40-nm standard CMOS technology.The simulation results show that the stability of SE-8Tis high while the power consumption is low.Therefore,the power consumption of the proposed SE-8T based approximate SRAM is very low.At 0.5Vsupply voltage,the power consumption of proposed approximate SRAM is 59.86%less than that of conventional 6T under the same operation frequency.