基于40nm CMOS工艺的高效率功率放大器设计

Design of a High Efficiency Power Amplifier Based on 40 nm CMOS Process

针对硅基毫米波功率放大器存在的饱和输出功率较低、增益不足和效率不高的问题,基于TSMC 40nm CMOS工艺,设计了一款工作在28GHz的高效率和高增益连续F类功率放大器。提出的功率放大器由驱动级和功率级组成。针对功率级设计了一款基于变压器的谐波控制网络来实现功率合成和谐波控制,有效地提高了功率放大器的饱和输出功率和功率附加效率。采用PMOS管电容抵消功率级的栅源电容,进一步提高线性度和增益。电路后仿真结果表明,设计的功率放大器在饱和输出功率为20.5dBm处的峰值功率附加效率54%,1dB压缩点为19dBm,功率增益为27dB,在24GHz~32GHz频率处的功率附加效率大于40%。

To solve the problem that silicon-based millimeter-wave power amplifier(PA)have low saturation output power,insufficient gain and low efficiency,a continuous class-F PA with high efficiency and high gain operating at 28 GHz was designed in TSMC 40 nm CMOS process.The proposed PA consisted of driver stage and power stage,where a transformer-based harmonic control network was designed to achieve power combining and harmonic suppression,which effectively improveed the saturated output power and power-added efficiency.Additionally,the PMOS capacitance was used to offset the gate-source capacitance of the power stage,further enhancing the linearity and gain.The post-simulation results show that the designed PA has a peak power-added efficiency of 54%at the saturated output power of 20.5 dBm,with the 1 dB compression point of 19 dBm,and power gain of 27 dB.In the frequency ranging from 24 GHz to 32 GHz,the power-added efficiency is greater than 40%.