期刊文献+

一种用于频率合成器的自动频率校正电路

Design of Automatic Frequency Correction Circuit for Frequency Synthesizer
下载PDF
导出
摘要 介绍了一种基于0.18μm标准CMOS工艺的自动频率校正电路,该电路采用开环粗调结构,使得频率合成器频率校正速度大大提高;采用编码预测性的二进制算法,使得频率校正的速度进一步提高。在电源电压3.3 V下进行仿真。结果显示,频率合成器的频率2150 MHz增加到2950 MHz,校正算法的控制码从0101变化到1111。可以看到自动频率校正算法的工作时间为48μs,随后锁相环开始工作,10μs后完成锁定过程。 Based on 0.18 μm CMOS process,an automatic frequency correction circuit was designed.The circuit adopts an open-loop coarse adjustment structure,which greatly increases the locking speed of the frequency synthesizer,and adopts a binary algorithm of coding predictability,so that the speed of frequency correction is further improved.Simulation was performed under a power supply voltage of 3.3 V,and the results showed that,frequency was change from 2 150 MHz to 2 950 MHz,capacitor array was change from 0101 to 1111.Frequency switching time is less than 58 μs,algorithm working time is 48 μs,PLL working time is 10 μs.
作者 邹奇峰 雷旭 廖鹏飞 ZOU Qi-feng;LEI Xu;LIAO Peng-fei(24^th Institute of China Electronics Technology Group Corporation,Chongqing 400060)
出处 《环境技术》 2020年第S01期56-60,70,共6页 Environmental Technology
关键词 二分法 自动频率校正 频率合成器 dichotomy automatic frequency correction frequency synthesizer
  • 相关文献

参考文献2

二级参考文献16

  • 1拉扎维·毕查德.模拟CMOS集成电路设计[M].西安:西安交通大学出版社,2003:345-346.
  • 2Hajimiri A, Lee T H. A General Theory of Phase Noise in Electrical Oscillators[ J ]. IEEE Journal of Solid- State Cireuits, 1998,33(2) :179 - 194.
  • 3Lesson D B. A Simple model of feedback Oscillator noise Spectrum[J]. Proceeding of the IEEE, 1966,54(2) :329 - 330.
  • 4Rael J J, Abidi A A. Physical processes of phase noise in differential LC oscillators[C] // IEEE Custom Integrated Circuits Conf. Orlando:[s, n.] ,2000:569 -572.
  • 5Razavi B. A Study of Phase Noise in CMOS Oseillators[J]. IEEE Journal of Solid- State Circuits, 1996,31(3) :331 - 343.
  • 6Hagazi E, Sjoland H, Abidi A. A Filtering Technique to low LC Oscillator Phase Noise[J]. IEEE Journal of Solid - State Circuits,2001,36(12) : 1921 - 1930.
  • 7Gardner F.Charge-pump phase-lock loops[J].IEEETransacations on Communications,1980,28(11):1849-1858.
  • 8Kyoohyun L,Chan-Hong P,Dal-Soo K,et al.Alow-noise phase-lock loop design by loop bandwidthoptimization[J].IEEE Journal of Solid-state Cir-cuits,2000,35(6):807-815.
  • 9Abassi S,Perrigo M E,Price C.Self-bias and differ-ential structure based PLL with fast lockup circuitand current range calibration for process variation:USA,6646512[P].2003-11-11.
  • 10Joonsuk L,Beomsup K.A low-noise fast-lock phase-locked loop with adaptive bandwidth control[J].IEEE Journal of Solid-state Circuits,2000,35(8):1137-1145.

共引文献5

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部