一种低压DDR终端调整器芯片

A Low Voltage DDR Terminal Regulator Chip

基于华宏0.35μmBCD工艺,设计了一种可以source(输出)和sink(吸入)电流的低压DDR(DoubleData Rate)终端调整器芯片。该芯片支持2.5 V输入电压轨和3.3 V输入电压轨。该芯片功率电源电压范围1.1 3.5 V,并且具备低噪声、低功耗、快速响应的特性,可以满足DDR、DDR2、DDR3、DDR3L、DDR4的VTT总线电压要求。仿真结果表明,最低工作电压达到2.375 V、空载静态电流只有800μA、source和sink电流达到3 A时,输出电压容差在±20 mV以内。

Based on Huahong 0.35 μm BCD process, a low voltage DDR(Double Data Rate)terminal regulator chip which can source and sink current is designed. The chip supports 2.5 V input voltage rail and 3.3 V input voltage rail. The power supply voltage of the chip is 1.1 V to 3.5 V, and has the characteristics of low noise, low power consumption and fast respond, which can meet the VTT bus voltage of the DDR、DDR2、DDR3、DDR3 L、DDR4. The simulation results show that the minimum operating voltage reaches 2.375 V,the quiescent current is only 800 μA and the output voltage tolerance is within 20 m V when the source and sink current reach 3 A.