摘要
采用65nm CMOS工艺设计了一款基于四路功率合成的77 GHz(E波段)功率放大器。采用电容中和技术抵消密勒电容的负面效应;利用功率合成技术解决MOS管低击穿电压引起的低输出电压摆幅的问题,将多路输出功率高效合成以实现高功率输出。采用共轭匹配和多频点叠加的带宽拓展技术,有效实现电路阻抗匹配和带宽拓展。后仿真结果表明,在79GHz处,该功率放大器的最大增益为20.5dB,-3dB带宽为64GHz~86GHz,输出功率1dB压缩点为12.7dBm,饱和输出功率16.6 dBm,峰值功率附加效率为16.5%。该功率放大器版图面积为0.29 mm^(2);在1.2V供电电压下,功耗为211mW。
A 77-GHz power amplifier(PA)with the four-way power combination has been designed using a 65-nm CMOS.The capacitance neutralization technique is used to offset the negative effect of Miller capacitance.The power combination approach is employed to solve the problem of low output voltage swing caused by low breakdown voltage of MOS transistors.Multi-output powers are efficiently synthesized to achieve high output power.Conjugate matching and bandwidth extension method based on the multi-frequency point superposition are adopted to realize circuit impedance matching and bandwidth expansion effectively.The post-simulation results show that the PA has a maximum gain of 20.5dB at 79GHz and its-3dB bandwidth covers from 64GHz to 86GHz.The 1dB compression point of output power is 12.7dBm,and the PA provides a saturated output power of 12.7dBm with a peak power added efficiency of 16.5%.The layout area is 0.29mm^(2),which consumes 211mW from a supply of 1.2V.
作者
纪忠玲
何进
王豪
常胜
黄启俊
JI Zhongling;HE Jin;WANG Hao;CHANG Sheng;HUANG Qijun(School of Physics and Technology,Wuhan University,Wuhan Hubei 430072,China)
出处
《电子器件》
CAS
北大核心
2022年第2期256-262,共7页
Chinese Journal of Electron Devices
基金
国家自然科学基金资助项目(61774113,61874079,62074116,81971702)