一种基于FPGA的任意时钟分频电路的算法与实现

An Algorithm and Implementation of Arbitrary Clock Divider Based on FPGA

为了得到控制电路中所需的各种不同的时钟频率,本文设计一种对FPGA内部时钟进行分频的通用算法。用Verilog语言描述电路时,将复杂的计算公式放在localparam语句中,由编译器来完成大量的计算。相比传统设计方法,该电路可获得一定精度的任意频率,消耗的电路资源更少。通过Modelsim仿真,下载到FPGA开发板上验证表明算法正确、有效,误差在可控范围内。

In order to obtain various clock frequencies required in the control circuit,a general algorithm for frequency division of FPGA internal clock is designed in this paper.When the circuit is described in Verilog language,the complex calculation formula is placed in the local param statement,and the compiler completes a large number of calculations.Compared with the traditional design method,the circuit can obtain any frequency with certain accuracy and consume less circuit resources.Through Modelsim simulation,it is downloaded to FPGA development board to verify that the algorithm is correct and effective,and the error is within the controllable range.