实数模型在闪存芯片验证中的应用

Real Number Modeling in Flash Memory Full chip Validation

NAND闪存比以往更需要大容量来满足日益增加的存储需求。在3D NAND时代,内部模拟控制和相关的开关转换电路更加复杂。同时,市场需要芯片更多的功能、更快的接口速度、以及更高性能的操作算法。然而,设计和验证的周期被压缩以适应激烈的竞争。传统的模拟或者快速模拟仿真无法快速地检查完整的芯片功能和特性,单纯的数字验证又无法有效地检查芯片的模拟行为。实数模型(RNM)是一种混合的验证方法,它借用了连续时域和分离时域的概念。电压和电流以浮点数的方式被建模,并且实数信号转换是在分离事件驱动下实现。仿真是在数字引擎下执行,且不需要模拟的解析器,这样就可以保证仿真高性能地执行。实数模型支持自定义类型(UDT)与自定义函数(UDR),可以实现不同的模拟行为。使用实数模型后,仿真可以覆盖几乎所有模拟信号的类型,从而监测更加准确的模拟行为。与完全的数字仿真相比,新方法并没有造成速度上明显的损失。

NAND flash memory is having larger density than ever before to meet growing huge demands of storage.During 3D NAND era,internal analog controls and switch circuits are more complex than ever before.Meanwhile chip with more functions,with higher IO speed,and with faster algorithm performance are required from market.But unfortunately,the design and validation periods are shrinking to survive the competitions.Traditional SPICE or fast SPICE simulation methodologies are unable to check full full chip functions and performances within schedule,and digital simulation is unable to cover any analog behaviors as well.Real Number Modeling(RNM)is a mixed approach,which borrows concepts from both continuous and discrete domains.Voltages and currents are modeled in terms of floating point number,and the real number changes per discrete trigger events.Simulation is performed in digital simulation engine without the need for analog solvers,which can make sure that simulation launch with high performance.RNM supports user-defined-type(UDT)and user-definedresolution(UDR),which can meet requirements of different analog behaviors.By using RNM technology in 3D NAND full chip validation,simulation can cover almost all types of analog signals,and therefore more correct analog behaviors could be monitored.Compared to complete digital simulation in Verilog simulator,there is almost no noticeable speed sacrifice.