紧凑型大驱动周期干扰发生器设计

Design of compact large driving period interference generator

为了降低目前的集成电路电磁干扰测试实验成本及风险,提出了一种可以对低阻抗集成电路芯片电源端进行周期性扰动的干扰发生电路。该电路使用低阻抗MOS管作为输出驱动,将多个MOS管连接到不同输出电压值的电源芯片上,使用FPGA控制这些MOS管的开关,能够产生具有一定频率与幅值的周期性扰动波形。以该电路结构制成的干扰器能以板卡的形式插到测试板上,用普通充电器即可供电,相对射频信号源加功率放大器这样的大型装备,其具有体积小、功耗低、操作简单、造价低,安全方便等特点。将干扰器接入用于等效低阻抗待测芯片的负载电路进行电磁干扰实验测试。测试结果表明,干扰器可以对电容值为50 pF,电阻值为10Ω的低阻抗负载,在0~30 MHz范围内,产生约1 V的电压扰动,在30~80 MHz范围内,产生0.5~1 V的电压扰动。

In order to reduce the cost and risk of current integrated circuit electromagnetic interference test experiment,an interference generating circuit which can periodically disturb the power supply end of low impedance integrated circuit chip is proposed.The circuit uses low impedance MOS tubes as the output driver,connects multiple MOS tubes to power chips with different output voltage values,and uses FPGA to control the switches of these MOS tubes,which can produce periodic disturbance waveforms with certain frequency and amplitude.The jammer made of the circuit structure can be inserted into the test board in the form of board card and can be powered by ordinary charger.Compared with large equipment such as RF signal source and power amplifier,it has the characteristics of small volume,low power consumption,simple operation,low cost,safety and convenience.The jammer is connected to the load circuit of the chip to be tested with equivalent low impedance for electromagnetic interference test.The test results show that the jammer can generate about 1 V voltage disturbance in the range of 0~30 MHz and 0.5~1 V voltage disturbance in the range of 30~80 MHz for low impedance load with capacitance of 50 pF and resistance of 10Ω.