基于FPGA的SM2点运算快速并行实现

Implementation of parallel and fast SM2 point calculation on FPGA

有限域椭圆曲线的点加以及倍点是国密SM2算法的核心运算,运行速度决定了SM2算法的整体性能。针对GF(p)点运算传统串行调度方法性能较低的问题,提出采用三路并行架构加速点运算实现,并分析不同并行架构下的加速性能及瓶颈。针对传统并行算法加速性能受到关键运算数据依赖性制约的现象,提出点运算间预计算优化机制,减少数据依赖性对运算并行化的制约,优化调度算法效率。基于FPGA平台实现改进后的并行调度算法,点运算所调用的底层模乘运算采用大数分治乘法算法配合快速模约减模实现,在8个周期完成p256素域模乘运算。硬件仿真表明提出的点运算调度算法效率相比现有并行方案提升20%,基于并行架构的点乘运算运行时间降低至221μs,相较同类实现具有明显性能优势。

Point addition and double on elliptic curve over finite field are core operations of SM2 algorithm,and calculation speed determines the overall performance of SM2.Due to low performance of traditional serial scheduling algorithms,purpose a three-way parallel scheduling algorithm and analyzes acceleration rate and bottleneck of different parallel architects.Besides,a pre-calculation mechanism between point calculation rounds is proposed,to reduce restriction of critical paths on parallelism and accelerate point multiplication.Implementing modified parallel schedule on FPGA platform,with modular multiplication bases on multiplication of large number and fast modular reduction,which calculates modular multiplication over prime field p256 within 8 clock cycles.The hardware simulation shows that the efficiency of calculation schedular algorithm 20%higher than that of the existing parallel schemes.And the time of point multiplication is reduced to 221μs,which has obvious performance advantages over similar implementations.