兼容bfloat16的高速浮点加法器设计

Design of high speed floating-point adder with bfloat16

为了提高人工智能、深度学习等领域对于浮点数计算的速度,介绍了一种兼容bfloat16格式的高速浮点加法器,在可以完成正常格式的16、32、64位浮点数计算,同时兼容bfloat16格式浮点数进行计算,利用对应的浮点加法指令编写定向测试激励进行功能验证,对设计结果利用软件综合验证。设计使用主流的双通路TWO-PATH算法,即根据阶码差值大小将计算转化为不同路径计算,首先为减少计算绝对延时,调整计算步骤缩减流水线拍数;然后在半精度加法中实现兼容bfloat16格式。相比于初始设计频率下降1.36%,为2.16 GHz,面积增加14.01%,功率增加53.31%。

In order to improve the speed of floating-point calculations in artificial intelligence,deep learning and other fields,a high-speed floating-point adder compatible with bfloat16 format is introduced,which can complete normal format 16,32,64-bit floating-point calculations,and is compatible with bfloat16 format.Floating-point numbers are calculated,the corresponding floating-point addition instructions are used to write directional test stimuli for functional verification,and the design results are comprehensively verified by the software.The design uses the mainstream dual-path TWO-PATH algorithm,which converts the calculation into different path calculations according to the magnitude of the order code difference.First,to reduce the absolute delay of the calculation,the calculation steps are adjusted to reduce the number of pipeline beats;then the compatibility is achieved in the half-precision addition bfloat16 format.Compared with the initial design frequency,the frequency is reduced by 1.36%to 2.16 GHz,the area is increased by 14.01%,and the power is increased by 53.31%.