基于UVM的SDIO接口的验证平台搭建

Construction of a UVM-Based Verification Platform for SDIO Interface

如今芯片的功能日渐增多且愈发难以理解,运用仿真器的波形去验证设计变得越来越困难,为了缩短简化验证时间,需要提供一个标准化的验证平台。因为电阻晶体管逻辑(Resistor Transistor Logic,RTL)的代码使用的是Verilog语言,但是验证没有标准化,不能够重复利用,而UVM正好可以提供验证平台的标准化,因此目前更多选择统一验证方法学(Universal Verification Methodology,UVM)作为验证平台。安全数字输入输出卡(Secure Digital Input and Output Card,SDIO)接口在消费电子产品中的应用极为广泛,特别是在为各类移动设备提供低能耗与高速度的数据存储及应用功能方面。本研究利用UVM验证平台,专注于系统芯片(System on Chip,SoC)芯片内SDIO接口的特定功能,开发并构建了一套适配被测设备(Device Under Test,DUT)的验证平台。该平台能够生成受限制的随机测试激励,并采用覆盖率作为衡量验证进展的标准。

As chips grow more powerful and harder to understand,verifying designs through simulator waveforms is becoming more challenging.To shorten and simplify the verification process,a standardized verification platform is essential.The Resistor Transistor Logic(RTL)code utilizes Verilog language,but the lack of standardization in verification impedes reuse.However,Universal Verification Methodology(UVM),offers standardization for verification platforms,making it a popular choice.The Secure Digital Input and Output Card(SDIO)interface is extensively used in consumer electronics,providing low-power and high-speed data storage and application functions for various mobile devices.This paper utilizes the UVM verification platform,tailored to the functional characteristics of SDIO interface in System on Chip(SoC).It describes the design and construction of a verification platform suitable for Device Under Test(DUT),along with the development of constrained random test stimuli,and evaluates the progress of verification through coverage rates.