FinFET芯片TEM样品制备及避免窗帘效应方法

Preparation of FinFET Chip TEM Sample and Method to Avoid Curtaining Effect

制备高质量纳米尺度芯片透射电子显微镜(TEM)样品对于探索半导体器件结构设计、材料分布与芯片性能之间的关系具有重要的意义。使用聚焦离子束(FIB)/扫描电子显微镜(SEM)双束系统制备14 nm鳍式场效应晶体管(FinFET)截面TEM样品,制备过程中从技术角度提出了两种自下而上制样方案来抑制窗帘效应。为扩大样品的可表征视场范围,在避免样品弯曲的前提下,提出了一种薄片提取方法。结果表明,离子束流越大,窗帘效应越严重,自下而上方法能有效规避窗帘效应;离子束电压30 kV时采用清洗截面(CCS)模式、5 kV/2 kV时采用矩形模式,样品台倾斜补偿角度为1.5°~3.5°,进行交叉减薄,且最终铣削长度控制在1μm时减薄效果最好;新的薄片提取方法改变了样品的铣削方向,在避免窗帘效应破坏感兴趣结构和样品弯曲的前提下,将样品的可表征视场范围扩大了5倍。研究结果对优化TEM样品制备方法以及芯片失效分析提供了参考。

The preparation of high quality transmission electron microscope(TEM)samples with nanoscale chip is of important significance for exploring the relationships among the structural design of semiconductor devices,material distribution and chip performance.The cross-sectional TEM samples of 14 nm fin field effect transistor(FinFET)was prepared by a focused ion beam(FIB)/scanning electron microscope(SEM)dual-beam system.Two bottom-top sampling schemes were proposed to suppress the curtaining effect from a technical point of view range during the preparation process.To expand the characterizable field of view range of the sample,a method of thin slice extraction was proposed on the premise of avoiding sample bending.The results show that the larger the ion beam current,the more serious the curtaining effect,and the bottom-top method can effectively avoid the curtaining effect;the best thinning process is to set cleaning cross section(CCS)mode for ion beam voltage of 30 kV and rectangle mode for 5 kV/2 kV with a tilt compensation angle of sample stage of 1.5°-3.5°.By cross thinning,the best thinning effect is achieved when the final milling length is controlled at 1μm.The new thin slice extraction method changes the milling orientation of sample,and extends the characterizable field of view range of the sample by 5 times on the premise of avoiding the curtain effect damage to the structure of interest and sample bending.The research results provide the reference for optimizing preparation methods of TEM samples and failure analysis of chips.