基于RISC-V指令集的向量控制模块验证实现

Verification Implementation of Vector Control Module Based on RISC-V Instruction Set

RISC-V指令集架构具有永久开源、指令集精简且高效、处理器微架构模块化、架构扩展性强等特点,在云计算、边缘计算、车载智能计算等领域的应用日渐广泛,其向量扩展部件可以大幅度提高计算机的运算效率,减少不必要的硬件开销.随着处理器运算能力增强和寄存器位数扩展等硬件的进一步发展,向量部件已成为处理器芯片架构中的常用技术,可用来增强处理器性能.向量控制模块是向量部件的核心控制单元,具有时序关系复杂、规范难以描述等特点.本文针对向量控制模块特点,优化设计验证流程,构建高效率验证平台,以功能覆盖率和代码覆盖率为牵引量化验证进度.通过RISC-V向量控制模块验证,有效提升向量控制模块的可靠性,降低流片风险,减轻子系统级验证和系统级验证负担,使之专注于互联、交互响应和接口验证.

RISC-V instruction set architecture has the characteristics of permanent open source,compact and efficient instruction set,modular processor microarchitecture,and strong architecture scalability.It is increasingly widely used in cloud computing,edge computing,and on-board intelligent computing.Its vector expansion unit can significantly improve the computing efficiency of computers and reduce unnecessary hardware overhead.With the further development of hardware such as processor computing power enhancement and register bit expansion,vector components have become a common technology in processor chip architecture to enhance processor performance.The vector control module is the core control unit of the vector component,which has the characteristics of complex timing relationship and difficult specification description.According to the characteristics of the vector control module,this research is aimed to optimize the design verification process by building an efficient verification platform,and taking functional coverage and structural coverage as the traction quantitative verification schedule.The verification experiment of RISC-V vector control module was made,and the results show that it can effectively improve the reliability of vector control module,reduce the risk of streaming and,reduce the burden of subsystem level verification and system level verification,and focus on interconnection,interactive response and interface verification.