基于FPGA的高速双通道数据队列管理实现

Implementation of High Speed Dual Channel Data Queue Management Based on FPGA

针对在高速宽带通信中经常使用到的数据帧队列管理与缓存功能,基于现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)设计并实现一种使用外置DDR缓存的多优先级的队列管理方案,结合FPGA运行特点,使用多接口并行处理方式提高处理速率,实现高速率数据帧优先级管理,通过功能仿真和实际硬件平台验证该方案可行性。

Aiming at the data frame queue management and cache function used in high speed broadband communication system,this paper designs a multi-priority queue management scheme using external DDR cache based on FPGA,considering the characteristic of FPGA,multi-interface input data is parallel processing to improve the processing speed.The implementation of high-speed data frame priority management,through the simulation and hardware platform to verify the feasibility of the scheme.