3LAU H T. Overview and outlook of through-silicon Via ( TSV ) and 3D integrations [J]. Microelectronics International, 2011, 28 (2): 8-22.
4WU B Q, KUMAR A, PAMARTHY S. High aspect ratio silicon etch: a review [ J]. Journal of Applied Physics, 2010, 108 (5): 1101-1120.
5HONG S C, LEE W G, KIM W J, et al. Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking [J]. Microelectronics Reliability, 2011, 51 (12): 2228-2235.
6LAU J H, SOON W H, KUMAR A, et al. Fabrication of high aspect ratio TSV and assembly with fine-pitch low- cost solder microbump for Si interposer technology with high-density interconnects [J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2011, 1 (9): 1336-1344.
7RANGANATHAN N, PRASAD K, BALASUBRAMANIAN N, et al. A study of thermo-mechanical stress and its impact on through-silicon vias [ J ]. Journal of Micromechanics and Microengineering, 2008, 18 ( 7 ) : 5018 - 5030.
8FENG X, CAO I-I Y, YU H, et al. Study of internal stress on electroplating copper used in through silicon via filling [C] //// Proceedings of the 2011 InternationalConference on Electronic Packaging Technology and High Density Packaging. Shanghai, China, 2011: 1018- 1021.
9KWON W S, ALASTAIR T D, TEO K H, et al. Stress evolution in surrounding silicon of Cu-filled through- silicon via undergoing thermal annealing by multi- wavelength micro-Raman spectroscopy [ J]. Applied Physics Letters, 2011, 98 (23): 232106-232108.
10TRIGG A D, YU L H, CHENG C K, et al. Three dimensional stress mapping of silicon surrounded by copper filled through silicon vias using polychromator- based multi-wavelength micro raman spectroscopy [ J]. Applied Physics Express, 2010, 3 (8) : 086601 - 086603.
