基于Pezaris算法的流水线阵列乘法器设计

A Design of Pipeline Array Multiplier Based On Pezaris algorithm

介绍了补码阵列乘法器的Pezaris算法。为提高运算速度,利用流水线技术进行改进,设计出流水线结构阵列乘法器,使用VHDL语言建模,在Quartus II集成开发环境下进行仿真和功能验证。

The Pezaris algorithm of complement Array Multiplier has been introduced. For speeding up , it has been improved with the technique of pipeline. A N×N pipeline Array Multiplier has been designed with VHDL . The conclusion of Simulation and func- tion verification for it in the integration development environment of Quartus II has been given.