摘要
本文介绍了一种基于硬件描述语言VerilogHDL的背景噪声扣除电路设计,该设计与以往使用加减计数芯片组成的电路相比,具有与MCU接口简单,软件操作方便等优点。
A design of circuit which can deduct background noise based on VerilogHDL is introduced in this paper. Compared with the circuit used chips of the forward and backward counters , its interface with MCU is more simple and operation of software is more easy .
出处
《微计算机信息》
北大核心
2008年第2期282-284,共3页
Control & Automation
基金
国家自然科学基金资助项目(60538020)
