FPGA时钟分配网络设计技术

Design the Clock Distribution Network of FPGA

本文阐述了用于FPGA的可优化时钟分配网络功耗与面积的时钟布线结构模型。并在时钟分配网络中引入数字延迟锁相环减少时钟偏差,探讨了FPGA时钟网络中锁相环的实现方案。

In this paper, a usable architecture model of clock distribution network is presented for the optimization of power dissipation and area. The DLL(Delay Locked Loop)is then introduced to reduce the time skew and realize efficient clock distribution networks.