平台式FPGA中可重构存储器模块的设计

Design of a Reconfigurable Memory in Platform FPGA

可重构静态存储器(SRAM)模块是场可编程门阵列(FPGA)的重要组成部分,它必须尽量满足用户不同的需要,所以要有良好的可重构性能。本文设计了一款深亚微米工艺下的16-kb的高速,低功耗双端口可重构SRAM。它可以重构成16Kx1,8Kx2,4Kx4,2Kx8,1Kx16和512x32六种不同的工作模式。基于不同的配置选择,此SRAM可以配置为双端口SRAM,单端口SRAM,ROM,FIFO,大的查找表或移位寄存器,本文完整介绍了该SRAM的设计方法,重点介绍了一种新颖的存储单元电路结构:三端口存储单元,以及用于实现可重构功能的电路的设计方法。

The reconfigurable RAM block is a very important component of FPGA. To meet users’ many different application demands, the RAM block must provide good reconfigurable ability. A 16- Kb reconfigurable SRAM with high speed and low power assumption has been designed in this paper. Each block RAM supports multiple configurations or aspect ratios. It can be configured to six memory organizations, 16kx1, 8kx2, 4kx4, 2kx8, 1kx16, and 512x32. Using various configuration options, the RAM block creates dual port RAM, ...