基于FPGA的高速数据采集系统的设计

Design of a High-speed Data Acquisition System Based on FPGA

本文介绍了以FPGA为核心逻辑控制模块的高速数据采集系统。设计中采用了自顶向下的方法,将FPGA依据功能划分为几个模块,详细论述了各模块的设计方法和控制流程。FPGA模块设计使用VHDL语言,在XilinxISE中实现软件设计和完成仿真。整个采集系统不但可实现24路最大工作频率为500kHz的模拟信号采集,而且还能完成1路系统内部信号的采集以达到自校验功能。

The high-speed data acquisition system based on FPGA, which is the core logic control module of the system is introduced. According to the method of top-down, FPGA is divided into some functional modules. The designing method and controlling flow of each module are discussed in detail. The VHDL language is adopted in the FPGA module. Software design and system simulation are completed in the integration circumstance of Xilinx ISE. The system not only can acquire 24-route analog signals with 500kHz of maxima...