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基于路径成组分离策略的低功耗FIR设计

Low-Power FIR Design Based on Path Grouping Strategy
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摘要 本文通过对电路布局的多电压代价进行分析,提出把电路按照不同的路径长度成组分离为不同的区域时,易于采用多电压实现,且采用多电压实现的代价最小。并以剩余数系统为例进行仿真说明,在体系结构层得到具有不同时序约束的子模块,在电路层根据不同的路径长度分成两种不同的供电电压,达到降低功耗的目的。在实际应用中可以根据具体设计决定优化方案。 This paper analyze the multi-voltage cost of circuit placement, and present that only if the design can be partitioned to different domain according to different path length, the multi-voltage cost of placement is minimum and the design is easy to implement via multi-voltage. This paper takes the residue number system as example, result in sub-module with different timing constraint at the architecture level. And use dual voltage at the circuit to different part with different path length to reduce power. I...
出处 《微计算机信息》 北大核心 2008年第4期229-231,共3页 Control & Automation
基金 北京市科技计划重大项目"交互式有线数字电视信道传输核心技术开发"
关键词 低功耗 多电压 滤波器 时序约束 low-power multi-voltage filter timing constraint
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参考文献5

  • 1[2]Saraju p.Mohanty,N.Ranganathan,Design of a Low Power Image Watermarking Encoder using Dual Voltage and Frequency,18th International Conference on VLSI Design,pp.153-158,2005
  • 2[3]Gian Carlo Cardarilli,Alberto Nannarelli and Marco Re,Reducing Power Dissipation in FIR Filters using the Residue Number System,43rd IEEE Midwest Symposium on Circuits and Systems,vol.1,2000,p.320-323
  • 3[4]Yutai Ma,A Simplified Architecture for Modulo (2n+1) Multiplication,IEEE Transactions on computers,Vol.47,No.3,1998
  • 4[5]Andreas V.Curiger,Heinz Bonnenberg,Hubert Kaeslin,Regular VLSI Architecturesfor Multiplication Modulo (2n+1),IEEE Journal of Solid-State Circuits,Vol.26,No.7,pp990-994,July 1991
  • 5[6]Marco Re,Alberto Nannarelli,Gian Carlo Cardarilli,Roberto Lojacono,FPGA realization of RNS to binary signed conversion architecture,The IEEE International Symposium on Circuist and Systems (ISCAS 2001),vol.4,p350-353

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