低频数字相位(频率)测量的CPLD实现

CPLD REALIZATION OF LOW FREQUENCE DIGITAL PHASE MEASURE

以单片机和CPLD为核心,设计了低频相位(频率)检测系统。系统由CPLD相位频率测量模块、单片机和显示模块三个部分组成。利用VHDL语言设计了高速的测频测相模块,并下载到CPLD中,通过与单片机的独立接口,将测量到的数据传送到单片机中,由单片机完成计算和显示的功能。重点介绍了测频测相系统原理框图,CPLD中的测频测相模块原理框图,简要介绍了单片机控制程序、计算程序。采用CPLD配合单片机的设计方案,具有造价较低、速度高、精度高的优点,并且可以通过软件下载而达到仪器硬件升级的目的。

with SCM with CPLD for nucleus, designed the low frequency phase( frequency) detection system. That system is measured by the network of CPLD phase measure, SCM and display module three fractions constitutes. Using VHDL language designed the super-speed frequency phase measurement measures mold, combining downloading CPLD inside, passing the data to SCM with single a machine orifice, by SCM computing with the count function and the display. Introduce frequence phase measure system figure, frequence phase me...