高速数据压缩与缓存的FPGA实现

Implementation of High-Speed Data Compression and Data Cache with FPGA

本文设计了一种以FPGA为数据压缩和数据缓存单元的高速数据采集系统,其主要特点是对高速采集的数据进行实时压缩,再将压缩后的数据进行缓冲存储。该设计利用数据比较模块实时地将一个压缩比数组中的最大值保存起来,再将该最大值缓冲存储,从而满足采集系统的需要。文中分别设计了基于双口RAM和FIFO实现的两种缓冲方法,并对仿真结果进行了对比分析,该系统工作频率可达90MHZ。

A high-speed data acquisition system that uses FPGA as the data compression and data cache unit has been designed in this paper, the main point of this system is that it compresses the acquired data in time and then stores the compressed data in the cache. In order to meet the conditions that data acquisition needs, a data-comparing module is used to select the largest number in the compression ratio array, and then store the largest number in the cache. Two methods that based on dual-ports RAM and FIFO are...