摘要
采用CSM0.35μm CMOS工艺,设计了3.125Gbit/s4∶1复接器.系统采用树型结构,由两个并行的低速2∶1复接单元和一个高速2:1复接单元级联而成.低速单元采用带有电平恢复的传输管逻辑实现,高速单元采用动态传输门逻辑实现.具体电路由锁存器、选择器、分频器以及输入输出缓冲组成.复接器芯片面积为0.675mm×0.6mm.3.3V电源电压下,芯片整体功耗小于130mW,核心功耗是25mW.最高工作速率可达4Gbit/s.
This paper describes a 3.125Gbit/s 4∶1 multiplexer using CSM 0.35-μm CMOS process.The tree-type structure is adopted.The system is composed of two parallel low speed 2∶1 multiplexers and one high speed multiplexer.Level restoration pass-transistor logic is proposed for low speed cell while dynamic transmission gate logic for high speed cell.The concrete circuits are composed of latches,selectors,frequency divider and I/O buffers.Die area equals 0.675 mm×0.6 mm.The total power consumption of the chip is lowe...
出处
《电子器件》
CAS
2007年第2期411-414,共4页
Chinese Journal of Electron Devices
关键词
CMOS
复接器
低功耗
光纤通信
CMOS
multiplexer
low power
optical communication
