亚微米CMOS工艺中GG-NMOS结构ESD保护电路改进设计

An Improved Design of ESD Protection Circuit Using GG-NMOS Structure in Submicron CMOS Process

针对采用GG-NMOS结构ESD保护电路的IC芯片在实际应用中出现ESD失效现象,在不额外增加版图面积的情况下通过引入栅耦合技术对现有的ESD保护结构进行改进,并达到了预期效果.实验结果显示其性能达到了人体放电模式的2级标准(HBM:3000V),机器模式3级标准(MM:400V).

In practical application,the IC which uses the ESD protection circuit of GG-NMOS structure might fail in some occasions.Aiming at this phenomenon,the current ESD protection circuit which uses GG-NMOS structure is mended by introducing the gate-coupled technology without increasing layout area.The following experiment shows that the ability of the improved circuit achieves class 2 of the human-body model(HBM:3000 V)and class C of the machine model(MM:400 V).