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集成双层平面电感的单片DC/DC转换器设计 被引量：1

Double-Layer Planar Inductor Based Fully Integrated DC/DC Converter
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摘要 采用0.35μm标准CMOS工艺设计了3.3V/1.5V单片低压Buck转换器,开关频率为150MHz.本文采用了电压型脉宽调制的反馈控制模式,克服了频率提高所带来的转换器系统不稳定问题.对双层平面螺旋电感进行了设计与优化,获得品质因数2.6,电感值28nH的双层平面电感.模拟结果表明,对应于不同输入电压或不同负载,转换器系统工作稳定,输入调整率-40dB,输出调整率-60dB.输出电压纹波平均值可以控制在额定值75mV,转换效率71%. A monolithic low-voltage 3.3 V/1.5 V Buck converter with the switching frequency of 150 MHz was designed in 0.35 micron CMOS technology.The voltage feedback pulse-width modulation control model was used to overcome the instability of the converter system because of the high switching frequency.A double-layer spiral inductor is designed and optimized,quality factor of 2.6,and inductance of 28 nH was obtained.From the simulated results,the stability of the designed monolithic Buck converter with different inp...
作者 李清华 邵志标 张春茗 耿莉
机构地区 西安交通大学微电子研究所
出处 《电子器件》 CAS 2007年第2期487-490,共4页 Chinese Journal of Electron Devices
基金 国家自然科学基金项目资助(60206003)
关键词 单片Buck转换器 双层平面电感器 转换效率 调整率 输出电压纹波 monolithic Buck converters double-layer planar inductor power efficiency regulation output voltage ripple
分类号 TM46 [电气工程—电器]
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参考文献9

  • 1[1]Musunuri S,Chapman P L,Zou J,et al.Design Issues for Monolithic DC-DC Converters[J].IEEE Trans.on Power Electronics,2005,20(5):639-649.
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同被引文献10

  • 1Nguyen N M,Meyer R G.Si IC-compatible Inductors and LC Passive Filters[J].IEEE Journal of Solid-State Circuits,1990,25(4):1 028-1 031.
  • 2Long J R,Copeland M A.The Modeling,Characterization,and Design of Monolithic Inductors for Silicon RF IC's[J].IEEE Journal of Solid-State Circuits,1997,32(3):357-369.
  • 3Gao Wei,Yu Zhiping.Scalable Compact Circuit Model and Synthesis for RF Spiral Inductors[J].IEEE Trans on Microwave Theory and Techniques,2006,54(3):1 055-1 064.
  • 4Li Qinghua,Geng Li,Shao Zhibiao.A Monolithic Low-power Buck Converter Integrated in CMOS Process[C]//Proc of APMC 2005.New York:IEEE,2005:896-899.
  • 5Boyd S,Kim S J,Vandenberghe L,et al.A Tutorial on Geometric Programming[EB/OL].[2005-12-26].http://www.stanford.edu/～boyd.html.
  • 6Mar Hershenson M,Mohan S S,Boyd S P,et al.Optimization of Inductor Circuits Via Geometric Programming[C]//Proc of 36th Design Automation Conference.New York:IEEE,1999:994-998.
  • 7Zolfaghari A,Chan A,Razavi B.Stacked Inductors and Transformers in CMOS Technology[J].IEEE Journal of Solid-State Circuits,2001,36 (4):620-628.
  • 8Mohan S S,Hershenson M M,Boyd S P,et al.Simple Accurate Expressions for Planar Spiral Inductances[J].IEEE Journal of Solid-State Circuits,1999,34 (10):1 419-1 424.
  • 9Li Qinghua,Geng Li,Shao Zhibiao.Optimum Double-layer Spiral Inductor on Silicon Substrate Designed for Monolithic Buck Converters[C]//Proc of APMC 2005.New York:IEEE,2005:2 156-2 159.
  • 10Yue C P,Ryu C,Lau J,et al.A Physical Model for Planar Spiral Inductors on Silicon[C]//International Electron Devices Meeting 1996.New York:IEEE,1996:155-158.

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电子器件
2007年 第2期

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