一种串行Viterbi译码器的FPGA设计与实现

FPGA Design of Serial Viterbi Decoder

介绍了基于超宽带(UWB)通信系统的(2,1,6)卷积码和Viterbi译码基本原理,设计了串行Viterbi译码器以及各个子模块实现电路,采用Altera公司的Apex20ke系列FPGA来综合实现,完成了Viterbi译码器硬件设计.该设计使用串行结构,回溯算法,占用LEs仅2195个,与并行译码相比节省了约50%的硬件资源.

The theory of(2,1,6) convolutional encoding and Viterbi decoding based on UWB(Ultra Width Band) communication system is introduced.Simultaneously,the implementing circuit of serial Viterbi decoder and its sub-module is accomplished.The hardware design of Viterbi decoder is implemented sucessfully in FPGA with Altera company s Apex20ke series.It adopts serial structure and traceback algorithm so as to only take up 2195 LEs in FPGA.Compared with parallel decoder,it saves about 50% hardware resouce.