一种高效的指令缓存单元架构及其性能分析(英文)

An Efficient Architechure of Instruction Cache Unit (ICU) with Emphasis on Its Performance Aanlysis

为了提高高速DSP或通用处理器的程序执行速度,描述了一种指令缓存单元的有效架构,特别是实现细节和性能分析.因所提出的指令缓存单元是为一种高性能VLIW结构的DSP核而设计,使用了并行的标签比较逻辑和寄存器堆的结构,芯片面积、关键路径延迟、功耗都大大减小.该指令缓存单元使用高层次的RTL(使用Verilog)编码,并由Synopsys的Design Compiler综合,使用不同的StarCoreTM基准程序测试比较,并进行性能分析.比较结果表明,所提出的结构是有效的,适合用于任何高速的处理器核.

This paper presents an efficient architecture of the Instruction Cache Unit(ICU) for enhancing the average execution speed of programs in any high speed DSP or general purpose processor Cores with emphasis on its implementation details and performance analysis.The proposed ICU is intended to be used in a high performance extended VLIW DSP Core;therefore it uses parallel tag comparison logic and register file based architecture to effectively reduce the chip area,critical path delay and power consumption.The...