一种新型双采样CMOS采样保持电路

Double-Sampling CMOS Sample-and-Hold Circuit

应用改进的双采样技术设计了一个标准CMOS模拟工艺下、采样率为80MHz的采样保持电路.应用单一时钟控制采样以消除两相采样的不匹配;采用时钟控制的双输入端运放以消除存储效应并消除大部分失调;采用栅压自举的采样开关以减小非线性失真.仿真结果表明,在2.5V电源电压下,当输入信号频率为37MHz时,采样保持电路可获得11bit的精度,消耗13mW的功耗.

Circuit level design of a new type double-sampling 80 Ms/s sample and hold circuit is realized in a standard CMOS analog process. Performing the sampling with a single switch is used to overcome the timing skew problem;Opamp with dual input controlling by clock is used to eliminate memory effect and most of the offset voltage;signal dependent clock bootstrapping switch is adopted to reduce the nonlinear error of the SHC. Simulation results demonstrate that the SHC consumes only 13 mW at 2.5 V supply with an...