一种用于数字集成系统的新型CMOS三态缓冲器的设计

Design of A Novel CMOS Three-State Buffer for Digital Integrated Systems

三态逻辑电路已被广泛应用于VLSI数字集成系统中.现在也有很多种实现三态逻辑的方法,但它们要么输出驱动能力不足够强要么占有较大的器件面积.在研究传统三态缓冲器的基础上设计了一种新型的三态缓冲器,据我们所知,这是使用晶体管数目最少的一种三态缓冲器结构.通过SPICE仿真实验表明,所设计的三态缓冲器与传统三态缓冲器相比具有更优的面积-延时积特性和更低的静态功耗.

The three-state logic is widely used in VLSI digital systems. There are many ways for realization of the CMOS three-state circuit. But they either take too much area or lack of the drive strength. A novel CMOS three-state buffer is proposed based on the research into traditional three-state buffers. To the best of our knowledge, this is a three-state buffer with minimum number of transistors. SPICE simulation demonstrates that the proposed three-state buffer presents optimum area-delay product characteristi...